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The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle...
Binary decision diagrams (BDDs) are the most frequently used data structure for handling Boolean functions because of their excellent efficiency in terms of time and space. Algebraic decision diagrams (ADDs) have been used to solve general purpose problems such as matrix multiplication, logic synthesis and formal verification. We propose a new type of BDD called weights binary decision diagram (WBDD)...
A new spectral method that eliminates the need of inner product evaluations in determination of signature of a combinational circuit realizing given Boolean function is described. The signature is obtained using probability coefficients of the function instead of conventional spectral signature. Theoretical relations for achievable computational advantage in terms of required additions in computing...
This paper presents a technique for representing multiple-output binary and word-level functions in GF(JV) (where N = pm, p is a prime number, and m is a nonzero positive integer) based on decision diagrams (DDs). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks, including integer multiplier circuits, and the results...
This paper propose a model for the complexity of Boolean functions with only XOR/XNOR min-terms using back propagation neural networks (BPNNs) applied to binary decision diagrams (BDDs). The developed BPNN model (BPNNM) is obtained through the training process of experimental data using Brain Maker software package. The outcome of this model is a unique matrix for the complexity estimation over a...
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