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The on-chip instruction cache is a potential power hungry component in embedded systems due to its large chip area and high access-frequency. Aiming at reducing power consumption of the on-chip cache, we proposed a Reduced One-Bit Tag Instruction Cache (ROBTIC), where the cache size is judiciously reduced and the cache tag field only contains the least significant bit of the full tag. We developed...
Power consumption is a critical design issue in embedded processors. One common component in the processor is the register file (RF). RF takes a large portion of processor area and consumes a significant amount of power. This paper proposes a customization approach at the hardware description modeling level to reduce the register file power consumption. The customization does not alter the RF interface...
This paper presents a bus coding methodology for instruction memory data-bus switching reduction. Compared to the existing state of the art multi-way partial bus-invert coding (MPBI) which relies on data bit-correlation, our approach is very effective in reducing switching activity for bus data, since little correlation can be observed on instruction data buses. Our experiments demonstrate the proposed...
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