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A novel feedback mechanism is proposed in this paper to enhance the performance of load-balanced two-stage switches. The key idea is to properly select and coordinate the two sequences of TV deterministic configurations used by the two stages of switch fabrics, thereby forming a joint sequence with both staggeredsymmetryproperty and in-orderpacketdeliveryproperty. With a single-packet-buffer-per-middle-stage...
A novel feedback-based two-stage switch architecture is presented in for solving the packet mis-sequencing problem in designing two-stage switches. With this architecture, each middle- stage port j piggybacks an N-bit VOQ occupancy vector to an output port k in each time slot. As output k and input k reside on the same line-card, input k schedules a packet for sending in the next time slot based on...
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