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A fully integrated THz phase-locked loop (PLL) is proposed. It is consists of a fundamental PLL and a frequency doubler. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the voltage-controlled oscillator (VCO). The wide locking-range divider chain of PLL consists of an injection-locked frequency...
This paper presents a configurable 1/2/3 order Butterworth low pass(LP)/complex bandpass (CBP) filter for sub-GHz Applications in a 180-nm CMOS process. The filter employs operational transconductance amplifier (OTA) unit with feedforward capacitor instead of conventional two-stage amplifiers to broaden bandwidth while consuming no extra power. In order to achieve a good noise figure, extra noise...
This paper presents a novel method to identify and boost difficult regions of in the configuration space (C-space) in changing environments. Difficult regions, especially narrow passages, change their shapes frequently in changing environments, which result in challenging problems to find valid and safe paths. Although a lot of research has been done to identify difficult regions, seldom methods provide...
Soft-start is very important for Boost converters to keep output voltage stable. However, previous methods may cause large initial inrush current, big voltage drop, overshoots and long start-up time. In this paper, the conventional resistor capacitor (RC) soft-start scheme is firstly analyzed, and then a novel soft-start strategy by using a variable ramp-slope with predefined voltage (VRSPV) is proposed...
In this paper, the power analysis and optimization are presented to aid the design of the pipeline analog-to-digital converters (ADC's). The dependency of the power dissipation on the main specifications of the analog-to-digital converters including the signal-to-noise ratio (SNR), the sampling rate, the power supply voltage, the effective stage resolutions, and the scaling index of the sampling capacitors...
A high output power and high efficiency power amplifier (PA) is designed for 60 GHz wireless point-to-point communication using IBM 90 nm CMOS process. A high efficiency is achieved through the utilization of cascode structure with floating n-well and differential inductor to resonate out the parasitic capacitances. To further boost the output power, four PA units are combined together through power...
A reconfigurable dual-band low noise amplifier (LNA) for 3.4-3.6 GHz IMT-Advanced and 4.2-4.8 GHz UWB systems is presented in this paper. Two different input matching networks with source-inductive-degeneration cascode configuration are used to switch at two different frequency bands. The parallel capacitors between the input MOSFETs' gate and source are used to optimize noise factor of the LNA. The...
This paper presents the design and analysis of a high linearity reconfigurable down-conversion mixer for IMT-Advanced (3.4~3.6 GHz) and UWB (4.2~4.8 GHz) applications. The proposed mixer is based on folded double-balanced Gilbert cell which is well-known for low voltage, simplicity and well-balanced performances. Capacitors are added parallel with the current generators to achieve the optimal IIP2...
A new double-sampling architecture is proposed for wideband low-power ΔΣ ADC design. A direct-charge-transfer adder is used to reduce the bandwidth requirements for the adder, and the loop filter's linearity requirement is relaxed by using a low-distortion topology. To verify the proposed design methodology, a 2nd order double-sampling delta-sigma ADC using the proposed scheme has been designed and...
A direct-charge-transfer adder is described for wideband low-power delta-sigma ADCs. Its operation and design are discussed in detail. Its application to noise-coupled delta-sigma ADCs is also described. To verify the proposed design methodology, a 2nd order noise-coupled delta-sigma ADC using direct-charge-transfer adder has been designed and simulated.
This paper presents a novel hybrid capacitor-clamp cascade 13-level inverter. The inverter is based on the series connection between two inverter modules with different dc bus voltage. It is the fact of a hybrid control scheme that higher voltage devices and faster devices operate in synergism. Subharmonic PWM method is employed in lower voltage module. In the case of three carrier dispositions, mathematic...
Use of multilevel converter has become popular in recent years. This paper presents a new topology of a hybrid capacitor-clamp cascade multilevel converter that is derived from two popular topologies. The new concept of the converter is based on the connection of multiple three-level capacitor-clamp converter modules with different DC bus voltages. With the novel topology consisting of higher voltage...
Use of multilevel converter has become popular in recent years. This paper will present a new topology of capacitor-clamp cascade multilevel converter that is derived from two popular topologies. The new concept of the novel capacitor-clamp cascade converter is based on the connection of multiple three-level capacitor-clamp converter modules. Nine level waveform of the proposed multilevel converter...
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