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Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption...
The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds...
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