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We have developed a thin, reliable, low-thermal-resistance LSI packaging technology by embedding a high-pin-count LSI chip into thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 μm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick...
Design techniques for an ultra-thin LSI package embedding a high-pin-count LSI chip in the thin package substrate have been developed to achieve the excellent electrical performance, as well as low warpage and high heat removal. The embedded chip package we designed is 27 mm by 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against...
We have developed a thin, low-thermal-resistance LSI package by embedding a high-pin-count LSI chip into ultra-thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 mum, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for...
We have developed a system-in-a-package (SiP) consisting of a sound source LSI and a speaker amplifier LSI for mobile applications, and have measured its signal-to-noise ratio (SNR). The sound source LSI chip is stacked on the speaker amplifier LSI chip with inserting a silicon spacer between these chips. Two types of interposers were applied to the SiP: one-metal polyimide tape and a two-metal glass...
This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results...
The authors describe an extremely-high-speed bipolar LSI technology. It uses 0.8- mu m-rule polysilicon emitter-base self-aligned, shallow-junction, and trench-isolation technologies. An LCML circuit with a minimum propagation delay time of 24 ps/gate has been realized at a gate current of 2.2 mA. The maximum cutoff frequency of the transistor is 30 GHz. The key process of the high-speed transistor...
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