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This paper proposes an efficient approach to deterministic static timing analysis, which uses relieved corner values for timing components of each gate to avoid the pessimistic estimates of the system delay. The candidates of the relieved corner values for timing components such as gate delay and output slew are sampled in terms of the input slew and the output capacitance, which composes the multi-corner...
We propose an analytic method to calculate the probability of timing violation of F/F-controlled paths by considering timing variations. We first characterize the timing characteristics of F/Fs and path delays using a generalized canonical delay model. The probability of setup-time violation is then calculated by considering the correlation between F/Fs and logic paths. For the calculation, we used...
This brief presents an efficient approach to statistical static timing analysis (STA), which estimates the system delay of statistical STA through deterministic STA. In statistical STA, the system delay is modeled as a function of random variables, so it is commonly expressed as a probability density function (pdf). Therefore, to estimate the system delay of statistical STA through deterministic STA,...
Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates...
Crosstalk noise is a critical issue in the deep submicron circuit design, since it causes functional failures in IC chips. This paper proposes an efficient approach to find the timing region of the circuit that timing failure occurs in an IC chip. The proposed method efficiently finds timing failure region by using CGOV metric without iterative simulations. In the experimental results, the proposed...
In this paper, we analyzes the error due to the effects of local random variation on delay and leakage in the gate level statistical modeling. In experiments with various gates, without considering the local random variation showed over 20% of maximum error on the gate delay standard deviation, when compared with the results considering the local random variation. Moreover, in the aspect of leakage,...
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