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Approximate computing has emerged as a new paradigm for energy-efficient design of circuits and systems. This paper presents a brief introduction to approximate computing as well as to the challenges faced by approximate computing with respect to its prospects for applications in energy-efficient and error-resilient computing systems.
Advances in CMOS technology have made digital circuits and systems very sensitive to manufacturing variations, aging, and/or soft errors. Fault-tolerant techniques using hardware redundancy have been extensively investigated for improving reliability. Quadded logic (QL) is an interwoven redundant logic technique that corrects errors by switching them from critical to subcritical status; however, QL...
This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row of PCM cells as reference. The threshold...
Effective fault tolerant techniques are crucial for a Network-on-Chip (NoC) to achieve reliable communication. In this paper, a novel VLSI architecture employing redundant routers is proposed to enhance the fault tolerance of an NoC. The NoC mesh is divided into blocks of 2×2 routers with a spare router placed in the center. The proposed fault-tolerant architecture, referred to as a quad-spare mesh,...
A single event causing multiple node upsets is a significant phenomenon for CMOS memories; its occurrence is due to the reduced feature size and the lower power supply voltage in the nanoscales. A low power memory cell that utilizes positive ground level voltage to reduce leakage power (requiring two transistors), is considered and two schemes are proposed for hardening. These designs require 4 additional...
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