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The programmability of the network data plane has become one of the most desirable features within the context of software defined networks, with P4 serving as a domain-specific language for defining data plane processing. In this work, we are motivated to address the challenges of mapping a P4 defined data plane to a heterogeneous programmable hardware architecture consisting of both a CPU and a...
The P4 language is an emerging domain-specific language for describing the data plane processing at a network device. P4 has been mapped to a wide range of forwarding devices including NPUs, programmable NICs and FPGAs, except for General Purpose Graphics Processing Unit (GPGPU) which is a salient parallel architecture for processing network flows. In this work, we design a heterogeneous architecture...
Analytics algorithms on big data sets require tremendous computational capabilities. Spark is a recent development that addresses big data challenges with data and computation distribution and in-memory caching. However, as a CPU only framework, Spark cannot leverage GPUs and a growing set of GPU libraries to achieve better performance and energy efficiency. We present HeteroSpark, a GPU-accelerated...
Emerging new network applications challenge the existing Internet infrastructure and call for flexible and open network facilities that can provide virtual networks for conducting experiments or deploying new services. In this paper, we propose to use hybrid multi-core processors including general purpose ones and network processors as the main processing elements of a programmable edge node (PEN),...
With the explosive growth in Internet traffic, requests have been overloading Web servers. Many ISPs and search engines employ a server cluster to build a cost-effective, scalable, and reliable server system. To make such a distributed-server system transparent to clients, architects usually place a switching device with one virtual Internet protocol (VIP) address in front of the server cluster as...
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