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In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate...
In recent high-density, high-speed and low-power VLSIs, soft errors (SEs) and delay faults (DFs) frequently occur. Therefore, SE hardened design and DF testing are essential. This paper proposes three types of scan flip-flops (FFs) which have SE tolerant capability and allow enhanced scan shifting for DF testing, i.e. arbitrary two-pattern testing. The slave latches used in these FFs are constructed...
This paper presents a high-speed low-density parity-check (LDPC) decoder chip using a new decoding algorithm, called a flooding-type update-schedule algorithm. Since node computations are performed using partially updated messages in the proposed algorithm, because of the good similarity among time-consecutive messages, data-transmission bottleneck between nodes for node computation is greatly reduced...
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