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In this paper, multiply-accumulator (MAC) is designed for application in simple 16-bit RISC processors to enhance the processor's capability by adding new instruction set. Creation of new instruction set is achieved by modifying the processor's architecture using Verilog Hardware Description Language (Verilog HDL). The new instruction set has simple structure, and can be fully compatible with the...
Unlike traditional SoC (System-on-chip) chip, multiprocessor chip that contains multiple independent processors, each processor owns different applications, so we need to make a reasonable multiprocessor chip initialization program. This paper proposes a design for the multiprocessor system initialization. The main contribution is as follows: Firstly, one method for the implementation of multiprocessor...
The FPGA performance of ciphers mainly includes area and throughput of implementation. In this design, several cryptographic algorithms such as SMS4, AES and Camellia have been implemented to analyze their performance and study the influence of the area with two different LUT-size FPGA devices. This paper uses VHDL to describe circuit function, choose Altera Stratix II and Cyclone II devices to simulation...
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