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We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position...
Thickness variations of ILD CMP induced yield loss at wafer edge is simulated by 3D Sentaurus Interconnect, in order to achieve more authentic condition, we adopt the image contour extraction technique to stream the genuine contact contour gds together with STI, POLY, ML database. The results demonstrates that when the thickness is over 7k at wafer edge, there is no electric current found, and it...
A band-pass-filter (BPF) based on silicon substrate was designed and simulated. Different software was applied to design and simulate the character of the filter. A three-order filter was designed dedicating to range 2.4 GHz-2.5 GHz use. The ideal topology circuit was designed with passive inductors and capacitors. Moreover, the integrated passive devices (IPDs) were modeled and simulated with thin...
With the increasing need of smaller size and lower cost of wireless communication system, the integrated passive devices (IPDs) have offered a proper solution. However, small Q factor (quality factor) of integrated passive inductors seriously limits the performance of the IPDs. In this paper, a simplified circuit model of the inductor structure has been presented to extract the parasitic parameters...
Poly-Si thin-film transistor (TFT) is the key building element for high-density 3D NAND Flash memory. Random grain boundary (GB) location and interface traps (Dit) density have been shown as the major root cause of variability [1]. However, with CNL pinned at midgap our previous model cannot adequately address experimental results - especially the cause of very low Vt TFT devices. In this work we...
With the increasing need of smaller size and lower cost of wireless communication system, the integrated passive devices (IPDs) have offered a proper solution. However, small Q factor (quality factor) of integrated passive inductors seriously limits the performance of the IPDs. In this paper, a simplified circuit model of the inductor structure has been presented to extract the parasitic parameters...
A band-pass-filter (BPF) based on silicon substrate was designed and simulated. Different software was applied to design and simulate the character of the filter. A three-order filter was designed dedicating to range 2.4 GHz-2.5 GHz use. The ideal topology circuit was designed with passive inductors and capacitors. Moreover, the integrated passive devices (IPDs) were modeled and simulated with thin...
In this study, a 3D package module based on flexible substrate is proposed. In order to improve the thermo-mechanical reliability of the 3D package module, the simulation of the key manufacture process is more and more important. The key manufacture processes of the 3D substrate package module mainly include 2D chip assembly, under-filling, 3D substrate folding, die-attaching, molding, and ball grid...
The electron and hole injection statistics of BE-SONOS NAND Flash is studied for the first time using a 75 nm charge-trapping NAND Flash test chip. By using the incremental step pulse programming (ISPP) method the impact of device variations are minimized and the electron number (N) fluctuation can be identified. We find that both electron and hole injection statistics well follow the Poisson statistics...
The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary...
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