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We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than −109 dBc/Hz...
A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency...
A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally...
A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X phases and Y phases can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V...
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