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Operating voltage (Vmin) improvement for High density SRAM with scaling is halted due to variability and aging effects which becomes a bottleneck for energy optimized operation. Device level and cell level advancements help the SRAM in lowering Vmin. Assist techniques become beneficial in Vmin lowering but due to BTI their Vmin degrades. BTI sensitivity analysis for these solutions gives insight of...
Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in...
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