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For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 µW/MHz active power and 82 % leakage power reduction.
We design a technique to separately measure the Vth of NMOS and PMOS. This technique is used to determine the body bias of NMOS and PMOS individually. Prototype chips with 1Mb 0.51 mm2 high-density SRAM cells using a 65 nm low-power process are fabricated and achieve 1.0 V operation, even when considering actual Vth variation.
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