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In high-κ (HfSiON and HfLaO) metal gate stacks, the traps leading to gate current Ig random telegraph noise (RTN) are found to be effectively passivated by bipolar switching from negative gate bias, where RTN and threshold voltage variation (ΔVT) are reduced significantly or even disappear. The reduction of RTN, ΔVT and Ig in degraded gate dielectrics is modeled by oxygen ion drift from the oxygen...
Dielectric breakdown in advanced gate stacks in state-of-the-art Si nanoelectronic devices has been one of the key front-end reliability concerns for further CMOS technology downscaling. In this paper, we present the latest findings in using physical analysis techniques such as transmission electron microscopy (TEM)/electron energy loss spectroscopy (EELS)/energy dispersive X-ray spectroscopy (EDS),...
In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO2) have been replaced by physically thicker high-κ transition metal oxide thin films by many manufacturers starting from the 45 nm technology node. CMOS process compatibility, integration and reliability are the key issues to address...
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