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This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft...
Emerging nonvolatile memory technology such as STT-MRAM (Spin Transfer Toque Magnetic RAM) is likely to become a promising technology to partly replace SRAM as embedded cache and to reduce the performance gap between the processor and cache. To take all advantages of STT-MRAM and SRAM, the use of STT-MRAM only and hybrid cache (SRAM & STT-MRAM) is investigated to construct new system hierarchies...
The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed,...
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