The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic...
As the physical gate length of current devices is reduced to below 65 nm, effects (such as large parametric variations and increase in leakage current) have caused the I-V characteristics to be substantially depart from those commonly associated with traditional MOSFETs, thus impeding the efficient development and manufacturing of devices at deep submicro/nano scales. Carbon Nanotube Field Effect...
There have been numerous nanowire crossbar architectures proposed till date and they are envisioned as clock-driven. To deal with numerous issues caused by clocking, a new asynchronous architecture based on Null Convention Logic (NCL) has been recently proposed, resulting in the removal of the clock circuit overhead from the crossbar architecture. The proposed architecture is easier to be manufactured...
As technology scales down in the deep sub-micron/nano ranges, CMOS circuits are more sensitive to externally induced phenomena to likely cause the occurrence of so-called soft errors. Therefore, the operation of these circuits to tolerate soft errors is a strict requirement in todaypsilas designs. Traditional error tolerant methods result in significant cost penalties in terms of power, area and performance,...
This paper presents a novel probability based analysis for leakage power estimation of partially-depleted silicon-on-insulator (PD-SOI) circuits. The proposed leakage power estimation algorithms is implemented in C language, and the proposed methodology is tested by ISCAS85 benchmark circuits designed in 100 nm SOI technology. The results show that the error is within 4% compared with Hspice Monte...
With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density systems consisting of nanometer-scale elements are likely...
Wave pipelining is a technique which can be used to speed up the circuit without insertion of storage elements, but because of that fact, needs to be more tightly controlled when being designed. This paper - taking the wave pipeline design constraints into account - looks to automate the generation of wave pipelined design netlists through synthesis and delay balancing scripts. The results show less...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.