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As processors migrate to multi- and many-core architectures, the role of the communication network becomes more important. Efficient communication architecture can drastically improve overall system performance. Taking into account the application behavior can facilitate system-level solutions that manage the communication cost. To address this issue, we propose a Clustered Globally Asynchronous Locally...
In this paper, we introduce a 3 valued MVCM 4-phase link, where cores at each end of the link use 4-phase dual-rail protocol. The dual-rail N-bit data are encoded onto N + 1 wires on the link, thus reducing the number of interconnects between cores and improving power and crosstalk features. We show that it is impractical to encode a 2-phase dual-rail asynchronous data bit onto one wire using MVCM...
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock synchronization, replication, or barrier synchronization. Among several multicast schemes proposed in on chip interconnection networks, path-based multicast scheme has been proven to be more efficient than the tree-based, and...
As nanotechnology scales down, the reliability issues are becoming more crucial, especially for Network-on-Chip (NoC) which must provide the communication requirements of Multi-Processor System-on-Chip (MP-SoC) even in presence of faults. In this paper we present a low cost faulty-link-tolerant routing algorithm through dynamic reconfiguration when the regular mesh topology is altered by faulty links...
In this paper, a novel adaptive routing model for avoiding congested areas through utilization of an adaptive routing table in two-dimensional mesh on-chip networks is proposed. The routing path is determined by minimizing a cost function which considers the path length and power consumption of the neighbor cores. The cells of routing table are updated dynamically by a coefficient which is a function...
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