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As CMOS technology scales down into the deep-submicron domain, the cost of design, complexity and customization for Systems-On-Chip (SoCs) is rapidly increasing due to the inefficiency of traditional CAD tools. In this paper we present a new interactive refinement algorithm in high-level synthesis, based on dynamic programming, which maximizes resource optimization in data path. We start by quantifying...
The stringent performance and area constraints and short time to market of modern digital systems drive us towards automated methods for producing high speed and low area architecture with optimum features. In this paper, we present a new algorithm, which automatically maximizes resource optimization of data path while meeting performance constraints. The main input of this algorithm is the control...
Asynchronous digital design approach liberates VLSI systems from clock signal and offers potential for low power and high performance design methods. Due to lack of commercial CAD tools, asynchronous circuit design has not been regarded with favor. To alleviate the situation, a SystemC library is developed as an extension to the existing SystemC language to enable asynchronous circuit description...
Model checking thoroughly verifies the design correctness with respect to a specification. When the verification process succeeds, we can only postulate the correctness of the design relative to the given specification. How far can we affirm the verified design implements all the behavior of the desired system? With this regard we need to estimate the completeness of the properties by using some coverage...
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