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In this paper we propose a novel framework for modelling heterogeneous SoC architectures with emphasis on reconfigurable component integration and optimised communication media. Our work targets three major issues faced by the current SoC design methodologies; a novel hybrid communication topology, communication centric platforms and modelling of reconfigurable components in the system. Multi-standard...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the design flow, in order to speed...
This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself...
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