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Photonic Networks-on-Chip (NoC) is considered as a promising candidate to interconnect a large number of processing cores. The heart of a photonic NoC is the on chip photonic interconnection network which is composed of silicon waveguides and optical routers. In this paper, we propose a scalable and non-blocking passive optical router design using micro-ring resonators (MRRs), namely the generic wavelength-routed...
In this paper, a simple, yet efficient hardware-based multicasting scheme is proposed for irregular mesh-based Network-on-Chips. First, an irregular oriented multicast strategy is proposed. Literally, following this strategy, an irregular oriented multicast routing algorithm can be designed based on any regular mesh-based multicast routing algorithm. One such algorithm, namely, Alternative XY (AL+XY),...
In our previous work, a multi-path routing (MPR) scheme was proposed to maximize the data throughput for torus-based NoCs by utilizing multiple paths for concurrent data transmission. In this paper, a deadlock-free virtual channel model is proposed for the MPR scheme. In this virtual channel model, every physical channel on the network is split into about 3.5 virtual channels on average. It is proved...
This paper presents a parameterized router design which can be applied to build large network-on-chips (NoCs) based on a Perfect Recursive Diagonal Torus (PKDT) or mesh/torus topology. In specific, the router is designed to support two routing algorithms (conventional vector routing and a newly proposed Johnson coded vector routing) and wormhole switching. Along these lines, special considerations...
In this paper, we present PRDT(2, 1), a new interconnection network topology for network-on-chip (NoC) design. PRDT(2,1) features a recursive structure, and has small diameter and average distance. We then focus our study on physical layout issues pertaining to PRDT(2, 1). Specifically, we show that the minimum number of metal layers required for the placement and routing in a PRDT (2, 1)-based NoC...
In this paper, we present a novel network topology to build an on chip interconnection network. This so called PRDT(2, 1) structure offers a few distinct architectural features, including (i) high scalability, (ii) small diameter and average distance, (iii) reconfigurability with its embedded mesh/torus topology, and (iv) high degree of fault tolerance. Routing in a PRDT(2, 1)-based network can be...
In networks-on-chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the increasing switching speed. The crosstalk between adjacent lines causes data dependent signal delay and noise, thus finally makes the communication channel unreliable. The crosstalk problem can be mitigated by wide spacing of...
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