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This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap...
This paper presents a new capacitor array architecture to achieve a 6 bit 550Ms/s energy-efficient SAR with 65nm CMOS, which also takes up smaller area than traditional SAR. The bypass logic is a key feature to speed up the SA algorithm. Dynamic logic is used in the critical path to accelerate the speed. The whole circuit is supplied with 1.2V voltage. Simulation results show that the SAR achieves...
A 1.1 mW 87 dB dynamic range 3rd order ΔΣ modulator is implemented in 0.18 μm CMOS technology for the audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed and only one simple current mirror single-stage OTA with 34 dB DC gain is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB...
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