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This paper describes a 64% locking-range type-I LC PLL architecture with a small loop filter area. By employing a dual-path LC VCO with a boosted open-loop gain at dc, a reference spur or a static phase error problem with a large frequency offset in the type-I PLL is alleviated. The prototype PLL is implemented in 0.13µm CMOS, achieving 2.74-to-5.37GHz locking range with <−50dBc reference...
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