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This work proposes an all digital clock generator (ADCG) with a new PVT compensation technique to generate a stable and accurate frequency over wide frequency ranges up to 8GHz. To compensate frequency variations by temperature changes, a novel Zero Temperature Coefficient (ZTC) algorithm using mutual compensation between the mobility and the threshold voltage of devices has been implemented. The...
As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been several approaches to convert analog systems to their digital counterparts and a high-resolution time-to-digital converter (TDC) is a key element for the digitalization of analog...
A fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. Features include adaptive bandwidth architecture, automatic frequency calibrator (AFC), a sub-1V V/I converter operation, feedback control to minimize charge-pump current mismatch, and a fully integrated loop filter. The whole PLL measures power consumption of 1.6mW when VCO oscillates...
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