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A reliability evaluation of a 300-mm-compatible 3DI process is presented. The structure has tungsten through-Si-vias (TSVs), a hybrid Cu/adhesive bonding interface, and a post Si-thinning Cu BEOL. The interface bonding strength, deep thermal cycles test, temperature and humidity test, and ambient permeation oxidation all show favorable results, indicating the suitability of this technology for VLSI...
In this paper a methodology based on fracture mechanics has been used to investigate the chip package interaction of ultra low-k/copper interconnect. When a wafer is diced into chips, defects can be generated at the edge of the chips. Under the thermal stress from the package the defects can propagate into the dielectric and cause the chip failure.
Ultra low-k (ULK, k=2.4) dielectric has weaker mechanical properties than first generation low-k films (k=3.0). The introduction of ULK into advanced back end of lines (BEOL) presents a significant challenge due to chip package interaction (CPI) where the packaged die is cycled over a temperature range and the resulting stress can cause ULK BEOL delamination. To avoid CPI failure detailed modeling...
A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep...
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