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Modeling and controlling of warpages and layout-dependent local-deformations are challenges to overcome to realize 3D stacking of dies with through-silicon vias and micro-bumps. Dies larger than about 500 mm2 are now being used for high performance computing, and large cylindrical warpage of the die and local die surface deformations can greatly affect the yield and reliability of the stacked dies...
Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along the sidewall, so-called scalloping, formed by Bosch etching, are strongly related to leakage currents between adjacent TSVs. Microcracks in the SiON barriers were observed by TEM analysis and correlated with the sidewall roughness. FEM simulations of the stress concentration along...
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