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In recent years, with the rapid development of the Internet, ever increasing traffic and link-bandwidths presented serious challenges for computer network-related research such as high-speed algorithm and development of high-performance network equipment. Of course, increasing complication in hardware, firewall filtering and Encryption technology, makes programmability getting more and more attention...
Due to the ever increased energy consumption, large research effort has devoted to the energy efficiency area. In this paper, a frequency scalable publish-subscribe filter forwarding node has been proposed and implemented for addressing this challenge. The frequency scaling filter can operate on three different frequencies, which adapts its capacity and power on different network throughput. Our work...
This paper presents a household electricity consumption algorithm, it has consumption limit warning function. The optimization objective is to automatically predict and adjust household appliances power consumption, control the total power consumption within the following thirty minutes. In order to simplify experiment, it was considered two kind of time adjustable appliances which have a high utilization...
This paper presents a low-power active RFID tag in UHF band. The tag introduces an additional co-processing digital circuit into the traditional microcontroller based active RFID tag. It consists of an ultra low power microcontroller, a co-processing digital circuit implemented on CPLD, a low power RF transceiver, micro-strip antenna and an on-board battery. The paper chooses MSP430F149, EPM240T100,...
This paper presents a low power LDPC decoder design based on reducing the amount of memory access. By utilizing the column overlapping of the LDPC parity check matrix, the amount of access for the memory storing the posterior values is minimized. In addition, a thresholding decoding scheme is proposed which reduces the memory access by trading off the error correcting performance. The decoder was...
In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation...
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