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Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on...
Polar codes under cyclic redundancy check-aided successive cancellation list (CA-SCL) decoding can outperform the turbo codes and the LDPC codes when code lengths are configured to be several kilobits. In order to reduce the decoding complexity, a novel tree-pruning scheme for the SCL/CA-SCL decoding algorithms is proposed in this letter. In each step of the decoding procedure, the candidate paths...
For polar codes with short-to-medium code length, list successive cancellation decoding is used to achieve a good error-correcting performance. However, list pruning in the current list decoding is based on the sorting strategy and its timing complexity is high. This results in a long decoding latency for large list size. In this work, aiming at a low-latency list decoding implementation, a double...
In this paper, we introduce two methods to implement clock synchronization in fiber channel. One is based on ELS (extended link service) transmission and the other is based on primitive signal transmission. Compared with the method based on ELS transmission, the primitive method is at least 20 times faster and consumes less power. Furthermore, we propose an area efficient method to implement encoding...
Partially parallel LDPC decoder is commonly used for practical applications due to its good tradeoff between the hardware cost and the throughput. In the partially parallel LDPC decoding architecture, two kinds of processor units are implemented: check node unit (CNU) and variable node unit (VNU). Because of the dependency between two kinds of processor units, the low hardware utilization efficiency...
This paper presents a low power LDPC decoder design based on reducing the amount of memory access. By utilizing the column overlapping of the LDPC parity check matrix, the amount of access for the memory storing the posterior values is minimized. In addition, a thresholding decoding scheme is proposed which reduces the memory access by trading off the error correcting performance. The decoder was...
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