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Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection techniques in high level synthesis use worst case delay/power information to perform the optimization, and therefore may be too pessimistic such that extra resources are used to guarantee design requirements. Parametric yield, which...
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed to facilitate DFT (Design-For-Test). Recently, three-dimensional (3D) technologies have been proposed as a promising solution to continue technology scaling. In this paper, we study the scan chain construction for 3D ICs,...
In this paper, we first explore sub-threshold Fin-FET circuits design space, finding their optimal power supply point for minimum energy consumption. We then study soft error vulnerability in sub-threshold region. Our experiments indicate that the energy consumption in sub-threshold region can achieve 4 orders of magnitude energy saving. Compared to bulk CMOS technology, FinFET circuits have lower...
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