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We discuss the commercial context and technical requirements to 100G coherent interfaces and illustrate ASIC design decisions and challenges, looking beyond 100G as well.
We report the measured WDM performance of a real-time 120 Gbps coherent PM-QPSK MSA transceiver with industry-first integrated ADC, DSP and SD-FEC in a 40nm CMOS ASIC. We also evaluate MPI induced OSNR penalty.
We report error-free, 47×80km transmission of a real-time, 120Gbps, coherent PM-QPSK MSA transceiver with soft-decision forward-error-correction. Two cascaded commercial systems included 40G neighbors and ten ROADMs. The transceiver compensated 60,000ps/nm and had 2.5dB remaining margin.
We demonstrate a 120 Gb/s coherent polarization-multiplexed quadrature-phase-shift-keyed transceiver with soft-decision forward-error-correction (SD-FEC) coding based on Turbo Product Code. This industry-first transceiver module utilizes a 40 nm complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit with integrated analog-to-digital conversion, digital signal processing...
We demonstrate the generation of a 1.12-Tb/s superchannel with a net intrachannel-spectral-efficiency (ISE) of 8.6 b/s/Hz, and its transmission over a 76.8-km seven-core-fiber using space-division-multiplexing, achieving a record aggregate ISE of 60 b/s/Hz per fiber.
We demonstrate 2688-km multi-span transmission using wavelength-division multiplexing (WDM) of ten 50-GHz spaced 128-Gb/s PDM-QPSK signals, space-division multiplexed (SDM) in a low-crosstalk 76.8-km seven-core fiber, achieving a record net aggregate per-fiber-spectral-efficiency-distance product of 40,320 km-b/s/Hz.
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