The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, we propose a novel saliency model for stereoscopic images. To improve depth information for stereo saliency analysis, this model exploits depth information from three aspects: 1) we extract the low-level features based on the color-depth contrast features in a local and global search range (local-global contrast); 2) to extract the topological structural from a depth map, a surrounding...
This paper focuses on the visual fatigue issue while viewing 3D contents. The issue is caused by the distance between the screen and the fused images. A stereo image depth optimization system with disparity map calculation, viewpoint optimization and stereo image synthesis is proposed to solve the issue with the following procedure: first, its disparity map calculation adopts the modified binary window...
Three-dimensional (3D) vision measurement technology based on encoding structured light plays an important role and has become the main development trend in the field of 3D non-contact measurement. However, how to synthetically improve measurement speed, accuracy and sampling density is still a difficult problem. Thus in the present work, a novel 3D measurement method based on temporal encoding structured...
In this paper, we propose a test and repair architecture for 3D ICs consisting of stacked memory dies (slave dies) and a processor die (master die). The proposed architecture supports known-good-die (KGD) test, known-good-stack (KGS) test, and final test and repair. However, instead of incorporating spare elements in each memory die, a small-size redundant memory is incorporated into the processor...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.