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The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design...
The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce a redundant via allocation problem for layer partition-based model and solve it using genetic algorithm. The result of layer partition-based model depends on...
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