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A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528µm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell...
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