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Self-formed barrier technology using copper (Cu) manganese (Mn) alloy seed was applied for Cu dual-damascene interconnect with porous-SiOC/porous-PAr (k=2.3) hybrid dielectric for the first time. More than 90% yield for wiring and via-chain was obtained. 70% reduction in via resistance was confirmed compared with the conventional process. To estimate the moisture resistance property of self-formed...
Adhesion tests for a real Cu/low-k patterned structure were studied for 45-nm node devices. Results from 4 point-bending (4PB) and modified edge lift-off tests (m-ELT) were compared. Cu dual damascene interconnects structures with stacked hybrid low-k which is porous-poly-arylene(p-PAr)/porous-SiOC(p-SiOC) (k=2.3/2.3) were evaluated. Peel-off occurred in different locations in the real patterned structures...
A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k material in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that...
In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper (Cu) dual-damascene (DD) interconnects, a spin-on-dielectric (SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were successfully demonstrated. It was obtained that good via resistance and stress-induced voiding (SiV) reliability. In addition, CoW-cap and thin SiC (k=3...
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