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There is a method of global parametric faults location in analogue integrated circuits presented in this paper. Circuit Under Test is diagnosed in the time domain. The method is based on a utilisation of the tested device response and its derivative base features, i.e. following maxima and minima. The set consisted of base features is transformed into an advanced feature. Base features and the advanced...
This paper describes new method of fault diagnosis in analog electronic circuits (AEC). Fault diagnosis in analog electronic circuits is in general tested along with one dimension: the generator frequency. In this paper, we present a novel approach that uses more than one dimension to test AEC (those new dimensions are: the load resistance & reactance, generator resistance & reactance). Proposed...
This paper describes how increasing number of dimension of search space (in analog circuit diagnosis) can influence on identification of states of circuit under test (CUT). The criterion of optimization is the maximum number of identified states of CUT. In order to achieve this goal, first each state S and ambiguity set AS must be find and then optimized using Particle Swarm Optimization (PSO) algorithm...
An evolutionary technique for a linear analog circuit state recognition is presented in this paper. Transfer function zeros, poles and its amplification coefficient are determined by means of differential evolution. Time responses to a unit step stimulus for the circuit under test and for the evaluated phenotype are compared during the fitness calculation. Absolute response error of phenotype is minimized...
The method presented in this paper uses evolutionary computations to analog circuit testing stimulus shape optimization. The proposed testing excitation is a PWL waveform that generates responses of the tested circuit with appropriate relationship between current values of its specifications and the value of the observed parameter. The energy of error signal between nominal and actually obtained responses...
The testing and diagnosis catastrophic faults technique for analog high frequency (HF) circuits (passive filters and impedance matching circuits) is described in this paper. The novel method based on load and frequency as testing pair has been proposed. The impact of load on testing and diagnostic has been investigated. The best pairs of load and frequency have been chosen. The proposed approach of...
This article presents design of specialised aperiodic excitation. Purpose is improvement of fault diagnosis of analog electronic circuits. The goal is enhancement of catastrophic (hard) faults location. Further improvement is achieved after utilising additional feature extraction by means of wavelet transform. Obtained results are compared to fault diagnosis without feature extraction and diagnosis...
W artykule przedstawiono analizę wpływu globalnych uszkodzeń parametrycznych na odpowiedź analogowych układów scalonych (AIC) w dziedzinie czasu. Nowością jest wykorzystanie relacji oraz super-relacji pomiędzy wcześniej wspomnianymi cechami odpowiedzi układów. Przedstawiona metoda powinna pozwolić na zwiększenie testowalności oraz diagnozowalności globalnych uszkodzeń parametrycznych (GPF) w produkcji...
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