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There is a method of global parametric faults location in analogue integrated circuits presented in this paper. Circuit Under Test is diagnosed in the time domain. The method is based on a utilisation of the tested device response and its derivative base features, i.e. following maxima and minima. The set consisted of base features is transformed into an advanced feature. Base features and the advanced...
This paper describes new method of fault diagnosis in analog electronic circuits (AEC). Fault diagnosis in analog electronic circuits is in general tested along with one dimension: the generator frequency. In this paper, we present a novel approach that uses more than one dimension to test AEC (those new dimensions are: the load resistance & reactance, generator resistance & reactance). Proposed...
This paper describes how increasing number of dimension of search space (in analog circuit diagnosis) can influence on identification of states of circuit under test (CUT). The criterion of optimization is the maximum number of identified states of CUT. In order to achieve this goal, first each state S and ambiguity set AS must be find and then optimized using Particle Swarm Optimization (PSO) algorithm...
An evolutionary technique for a linear analog circuit state recognition is presented in this paper. Transfer function zeros, poles and its amplification coefficient are determined by means of differential evolution. Time responses to a unit step stimulus for the circuit under test and for the evaluated phenotype are compared during the fitness calculation. Absolute response error of phenotype is minimized...
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