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The concept and the simulated device characteristics of ultralow-power and high-performance band-to-band tunneling field-effect transistors employing stepped broken-gap heterobarriers, HetTFETs, are presented. Abrupt switching is defined by the onset of a band overlap. High on-state currents are provided by narrow tunnel barriers defined by crystal growth rather than electrostatics. Sentaurus Device...
This paper proposes a low-power variation - immune dual-threshold voltage CNFET-based 7T SRAM cell. The proposed CNFET-based 7T SRAM cell offers ~1.2× improvement in standby power, ~1.3× improvement in read delay, ~1.1× improvement in write delay. It offers tighter spread in write access time (1.4× @ OEP (optimum energy point) and 1.2× @ VDD=1 V). It features 56.3% improvement in hold static noise...
This paper presents the design of a wide bandwidth high performance CMOS realization of dual-output second generation current conveyor (CCII±) at 32nm technology node. HSPICE simulation shows that voltage and current bandwidths in excess of 10GHz are obtained, thus making the module quite suitable for applications in the microwave range of frequencies. Besides, the circuit is able to operate at reduced...
Content-addressable memory (CAM) is an essential component for high-speed lookup intensive applications. This paper presents a match-line selective charging technique to increase speed and reduce the energy per bit per search while increasing the noise-tolerance. Simulation in TSMC 0.18 μm technology with 64×72 Ternary CAM shows the match-line energy reduction of 45% compared to the conventional current-saving...
This paper investigates the prospects of mixed bundle of carbon nanotubes (CNT) as low-power high-speed interconnects for future VLSI applications. The power dissipation and delay of CNT bundle interconnects are examined and compared with that of the Cu interconnects at the 32-nm technology node. We evaluated and compared various performance metrics of interconnects with both CMOS and carbon nanotube...
This paper investigates subthreshold CMOS logic for ultra low power applications on next generation reconfigurable devices. The performance characteristics of key digital building blocks such as arithmetic units, multiplexers and look-up-tables have been analyzed in terms of speed, power dissipation and power delay product using Berkeley predictive technology models at 22 nm technology node for both...
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