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This paper describes an evaluation of Inhibition/Enhancement (In/En) network for noise robust automatic speech recognition (ASR). In articulatory feature based speech recognition using neural network, the In/En network is needed to discriminate whether the articulatory features (AFs) dynamic patterns of trajectories are convex or concave. The network is used to achieve categorical AFs movement by...
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we...
We suggest a new way for solving the minimum hitting set problem by using massive parallelism of light. The idea is to build a device which will generate all possible solution set and then selecting the correct one. The device has a graph like structure. There are several nodes connected by arcs (optical fiber). The light ray passing through an arc is delayed by some predefined time represented by...
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we...
We present a method of synthesizing ternary Galois field (GF(3)) based reversible/quantum logic circuits without any ancillary trits/qutrits and hence without any garbage outputs. We realize multi input ternary Toffoli gate and square functions of GF(3) variables using linear ion trap realizable Muthukrishnan-Stroud (M-S) gates and shift gates in the absence of ancillary qutrits. Then based on the...
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