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The authors presents a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI implemented in 65nm CMOS decreases power dissipation by 75% compared to that of a conventional LSI.
A 21-channel 8 Gb/s transceiver is implemented in a 90 nm CMOS technology. 168 Gb/s uncoded data transmission with 3.6 ns latency is achieved with 4-tap FFE, receiver equalization, jitter tolerant CDR and low jitter PLL. Measured bathtub plots for 80 cm FR-4 backplane indicate BER<10-15 with 0.11 UI phase margin at the nominal power consumption of 160 mW/ch.
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