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Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors...
With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of large scale integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale...
With the advent of super deep submicron age, the circuit performance is strongly impacted by the process variation. Power grid optimization which considers the timing error risk caused by the variation becomes very important for the stable and high-speed operation of the system. Most of conventional power grid optimization algorithms use the IR drop as their objective function. However, the real goal...
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