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The underground coal mine is dangerous environment with gas1. In long term operation, the insulation resistance of cable decreases, and then leads to leakage. This can result in a threat to human and production safety. The leakage fault signal is weak, and the protection methods have no selectivity. The improvement of the protection method for additional DC source is proposed in this paper. The leakage...
This paper presents an overview of the co-design technique for broadband RF ESD protection circuit designs. The unique mixed-mode ESD simulation design methodology allows full-chip design optimization and prediction of broadband RF ICs with full low-parasitic ESD protection, which were validated experimentally using ultra wideband (UWB) RF ICs and RF switch circuits in CMOS technologies.
This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify...
Electrostatic discharge (ESD) protection becomes essential to advanced integrated circuits (IC). Very fast IEC-ESD failure and protection design are emerging challenges for contemporary ICs, particularly for consumer and portable electronics. This paper presents a new mixed-mode IEC-ESD simulation-design method, which involves process, device, circuit and system level simulation to accurately address...
This paper discusses general procedures for simulation, design optimization, measurement and modeling of accurate and scalable on-chip RF spiral inductors in standard foundry CMOS for industrial applications. Electro-magnetic (EM) solver is used to simulate and optimize design of a library of inductors with various dimensions and specifications aiming to provide accurate and scalable inductors for...
CAD is essential to simulation, design and synthesis of on-chip ESD protection circuitry to ensure design prediction and verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and design methodology, including arbitrary ESD protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling...
RF ESD protection circuitry design emerges as a big challenge to RF IC design, where the main problem is associated with performance degradation of RF IC due to ESD-induced parasitics. It has been difficult to incorporate the ESD impacts into RF IC design due to lack of proper co-design approach and ESD device models. This paper presents a new ESD-RFIC co-design methodology, including RF ESD design...
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