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A novel quantum-dot cellular automata (QCA) design for the non-restoring binary array divider is presented, which is constructed using the proposed coplanar QCA Exclusive-OR gate and full adder. The results show that proposed designs have better performances than the best existing structures in terms of common design metrics. The presented 3 × 3 and 4 × 4 dividers are able to achieve 65, 75, 45% and...
The adder circuit is used as a main component in the multiplier circuits. The Baugh-Wooley, Braun and CSA multipliers are designed by using our proposed adder cell. The proposed adder circuit is designed by using Shannon theorem. The multiplier circuits are schematised by using DSCH2 VLSI CAD tool and their layouts are generated by using Microwind 3 VLSI CAD tool. The proposed adder based multiplier...
In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is designed by using multiplexing control input techniques. A combination of n- and p-transistors used on...
In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cells, used for various pass gates circuit design styles are evaluated in terms of area, propagation delay,...
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