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Variations in crosstalk is an added source of delay and glitch faults in system on chips built with deep sub-micron technology, especially in chips using wide and long buses. Many of these faults, in such sub-micron chips, may only appear when the chip works at normal operating speed. These crosstalk-induced faults are more serious in systems built with globally asynchronous locally synchronous principles...
This paper addresses communication optimisation for applications implemented on networks-on-chip. The mapping of data packets to network links and the timing of the release of the packets are critical for avoiding destination contention. This reduces the demand for communication buffers with obvious advantages in chip area and energy savings. We propose a buffer need analysis approach and a strategy...
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency...
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