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Effect of thermo-mechanical stress (TMS) originating from CuSn micro-bumps (µ-bumps) and Cu through-Si-vias (TSVs) on the retention characteristics of 20-µm-thick, vertically stacked dynamic random access memory (DRAM) chip has been investigated. At cumulative probability of 50 %, the retention period decreased nearly 47% for the DRAM chip having thickness value of 20 µm as compared to the retention...
Thinning down large scale integrated-chip (LSI) wafers to below 50 µm thickness is inevitable for the wafer-to-wafer (WtW) process as well as chip-to-wafer (CtW) or chip-to-chip (CtC) processes in three-dimensional LSI integration. In this work we have optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for WtW integration of 12-inch LSI wafer with thickness...
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