The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
3D integration is the most promising technology to enhance LSI performance beyond scaling theory. 3D LSIs have lots of advantages such as short wiring length, small chip size, and small pin capacitances, which leads to low power dissipation and high processing speed. However, there are still reliability problems to be solved. This paper describes mechanical stresses caused by Cu TSVs and CuSn microbumps...
Micro-Raman spectroscopic technique has been employed to study the induced stress/strain by the metal microbumps in 3D-LSI Si die/wafer after wafer thinning and bonding, and the impact of bump spacing, bump size, bonding temperature and bonding force in the stress distribution in such a microbump bonded LSIs has been investigated. It is inferred that (i) the Si present at the interface (between CuSn...
Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated...
Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5deg) polished silicon wafers by micro-Raman spectroscopy (muRS). The metal contamination in the thinned silicon substrates...
We develop novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/Sn bumps. Electroplated-evaporation bumping (EEB) technology, which is a combination of Cu electroplating and Sn evaporation, is developed to achieve uniform height of Cu/Sn bumps. We develop CMOS compatible dry etching processes for removing sputtered Cu/Ta layers to achieve small size and fine pitch...
A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were...
We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.