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An unique not-OR (NOR) flash memory cell using an asymmetric Schottky barrier (SB) was designed to increase programming speed and driving current. An asymmetric SB NOR flash memory cell was proposed on the basis of the fundamental structure of the conventional NOR flash memory cells with a length of 90 nm. The programming speed and the driving current of the SB NOR flash memory cell with an asymmetric...
An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.
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