The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A dynamic substructural method (DSM) is developed to simulate the board level drop test of a wafer level chip scale package (WL-CSP). Parametric study on package location at the test board, printed circuit board (PCB) thickness and WL-CSP package thickness is conducted in the board level drop test simulations. The peeling stress and first principle stress of the solder joints are checked and discussed...
This paper investigates the electromigration induced hillock generation in a wafer level interconnect structure through numerical approach. The electronic migration formulation that considers the effects of the electron wind force, stress gradients, temperature gradients, as well as the atomic density gradient has been developed. The parameter study for the Al line geometry with different width and...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.