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An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1–3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach)...
A promising method for controlling sheet resistance (Rs) of Cu interconnect through improved chemical mechanical planarization (CMP) endpoint capability was developed using broadband spectrometry together with feed-forward information from upstream process conditions. With this new method, the wafer-to-wafer (WTW) Rs range was reduced more than 50% compared to time-based CMP polish control.
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