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In a complex sequential circuit, the problem of fixing min-delay violations becomes more and more important. To our knowledge, no efficient approach is proposed to eliminate the min-delay violations in a layout-level implementation. In this paper, the min-delay violations in a layout-level implementation are considered. By using the available space along the routing wires, redundant loads can be inserted...
Based on the assumption of a single wiring open in a signal net, it is known that the non-tree topology for a signal net has no adjacent loop. In this paper, based on RC non-tree transformation in Elmore delay model, an optimal algorithm for timing analysis is firstly proposed to compute the timing delays of all the reference nodes in a non-tree topology. Compared with the SPICE tool, the experimental...
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